Ing. Jiří Kadlec, CSc.
Head of the department

Department:
Department of Signal Processing
Research interests:
Recursive system identification algorithms and AI inference algorithms; acceleration of computation on systems with processors and field programmable gate array on single device (AMD Zynq Ultrascale+ and AMD Versal); rapid prototyping of advanced signal processing algorithms suitable for microprocessor systems with specialised re-programmable accelerators on single chip. EU collaborative research in Chips JU projects.
Biography
Publication list
Position
since 2000 Senior researcher and head of the Department of Signal Processing
Long-term visits
1995 - 1996 Katholieke Universiteit Leuven, Belgium (6 months)
1992 - 1995 Queen's University of Belfast, UK
1990 University of Athens, Dep. of Physics (Humboldt Research Fellowship, 4 months)
1989 Ruhr University Bochum (Humboldt Research Fellowship, 1 year)
Partner in EU funded R&D projects
- Current EU R&D projects (Chips JU):
- SOIL - Solidify the European FDSOI Ecosystem Accelerating its Industrial Deployment (2024 - 2027)
- EECONE - European ECOsystem for greeN Electronics (2023 - 2026)
- Listen2Future - Acoustic sensor solutions integrated with digital technologies as key enablers for emerging applications fostering Society 5.0 (2023 - 2026)
- Past EU R&D projects:
- StorAIge (ECSEL JU, 2021 - 2024)
- Arrowhead Tools (ECSEL JU, 2019 - 2022)
- FitOptiVis (ECSEL JU, 2018 - 2021)
- WAKeMeUP (ECSEL JU, 2018 - 2021)
- Productive4.0 (ECSEL JU, 2017 - 2020)
- SILENSE (ECSEL JU, 2017 - 2020)
- THINGS2DO (ENIAC JU, 2014 - 2018)
- PANACHE (ENIAC JU, 2014 - 2018)
- EMC2 (ARTEMIS JU, 2014 - 2017)
- ALMARVI (ARTEMIS JU, 2014 - 2017)
- IDEAS (ENIAC JU, 2012 - 2015)
- AETHER (FP6 ICT, 2006 - 2009)
- RECONF 2 (FP5 IST, 2002 - 2004)
- HSLA (FP4 ESPRIT 1999 - 2002)
- Past EU specific support projects:
- Idealist2014, Idealist2011, Idealist7fp, Idealist34, Idealist-5fp, Idealist-East (1998 - 2014)
- COSINE and COSINE 2 (2005 - 2010)
- IST World (2005 - 2007)
- NetCeE and CEeB (2001 - 2003)
- Past national R&D projects:
- Centre for Applied Cybernetics (2000 - 2004)
- Centre for Applied Cybernetics II (2005 - 2011)
- Virtual Laboratory of Microprocessor Technology Application (2006 - 2011)
- Participation in the evolution of the standardization for embedded software for automotive industry (2004 - 2007)
- Past national support projects:
- OKO ICT Branch Contact Organization (2002 - 2016)
Professional activities:
1998 - 2020 Czech Delegate of ICT Programme Committee for EU R&D Framework Programmes
Books and chapters
- AETHER: Self-Adaptive Networked Entities: Autonomous Computing Elements for Future Pervasive Applications and Technologies, Reconfigurable Computing. From FPGAs to Hardware/Software Codesign, p. 149-184, Eds: Cardoso Joao, Hübner Michael Download DOI: 10.1007/978-1-4614-0061-5 [2011] :
- Virtuální laboratoř pro vývoj aplikací s mikroprocesory a FPGA, CERM (Brno, 2011) Download [2011] :
- Czech Republic, Information Society Technology, ÚTIA AV ČR (Praha, 1999) [1999] :
- Parallel implementation of restricted parameter tracking, Mathematics in Signal Processing, p. 315-325, Clarendon Press (Oxford, 1994) [1994] :
Journal articles
- Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project, Microprocessors and Microsystems 87 Download Download DOI: 10.1016/j.micpro.2021.104350 [2021] :
- ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA, Journal of Signal Processing Systems for Signal Image and Video Technology 91 1 (2019), p. 61-73 Download Download DOI: 10.1007/s11265-018-1424-1 [2019] :
- Účast České republiky ve společných technologických iniciativách ARTEMIS, ENIAC a ECSEL, Echo 2016, p. 12-14 Download [2016] :
- Účast ČR v projektech programu ICT HORIZONT 2020 v porovnání se zeměmi EU-13, Echo 2015, p. 11-15 Download [2015] :
- Zhodnocení účasti ČR v projektech priority ICT 7. RP v porovnání se zeměmi EU-12, Echo 3 (2014), p. 9-12 Download [2014] :
- Artemis JU and Eniac JU Projects with Czech Participation, Automa, p. 6-9 Download [2013] :
- Czech Companies Involved in the ARTEMIS Programme, Automa, p. 4-5 Download [2013] :
- Elektronika pro zvýšení bezpečnosti malých městských automobilů, Elektro 2013, p. 21-21 Download [2013] :
- Elektronika pro zvýšení bezpečnosti malých městských automobilů, Automa 19 2 (2013), p. 54-55 Download [2013] :
- Výsledky třetí výzvy programu společných technologických iniciativ ARTEMIS JU a ENIAC JU, Echo 2011 2 (2011), p. 18-19 Download [2011] :
- Účast ČR v programu informačních a komunikačních technologií (ICT) v 7. RP, Echo, p. 6-8, 15 Download [2010] :
- Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA, EURASIP Journal on Advances in Signal Processing 2008 2008 (2008), p. 1-11 Download DOI: 10.1155/2008/394201 [2008] :
- The European Logarithmic Microprocessor, IEEE Transactions on Computers 57 4 (2008), p. 532-546 Download [2008] :
- ARTEMIS - šance pro výzkum v oboru vestavných systémů - polemika, Automa 13 10 (2007), p. 13-15 [2007] :
- Podpora projektů informační a komunikační techniky v 7.rámcovém programu EU pro výzkum, Automa 13 5 (2006), p. 82-83 [2006] :
- Implementing floating-point DSP, Embedded Magazine 2 3 (2006), p. 12-14 Download [2006] :
- Platforma s částečnou dynamickou rekonfigurací FPGA, Automa 12 5 (2006), p. 40-43 [2006] :
- Význam účasti v projektech EU, Echo 2 2 (2005), p. 11-13 [2005] :
- Reconfigurable system on programmable chip platform, ATMEL Applications Journal, p. 9-12 [2005] :
- IDEALIST: Jak najít partnery pro projekty IST, Echo, p. 13 [2004] :
- Lattice for FPGAs using logarithmic arithmetic, Electronic Engineering 74 906 (2002), p. 53-56 [2002] :
- Vstup do evropské informační společnosti - program IST, Automa 6 7 (2000), p. 105-107 [2000] :
- Konkrétní příležitost pro firmy z ČR: Projekty take-up programu IST s termínem podání 31.10.2000, Automa 6 7 (2000), p. 104 [2000] :
- Arithmetic on the European Logarithmic Microprocessor, IEEE Transactions on Computers 49 7 (2000), p. 702-715 [2000] :
- Analysis of a normalized QR filter using Bayesian description of propagated data, International Journal of Adaptive Control and Signal Processing 13 6 (1999), p. 487-505 [1999] :
- A parallel fixed-point predictive controller, International Journal of Adaptive Control and Signal Processing 11 5 (1997), p. 415-430 Download [1997] :
- Transputer implementation of block regularized filtering, Kybernetika 32 3 (1996), p. 235-250 [1996] :
- The block regularised parameter estimator and its parallelisation, Automatica 31 8 (1995), p. 1125-1136 Download [1995] :
- Paralelní počítače a superpočítače dneška, Computer World 10 10 (1991), p. 18-19 [1991] :
Other publications
- Compilation of AI 3.0 models for Vitis 2023.2, AI 3.5 SW, AI 3.0 DPUCZDX8G (2024) Download [2024] :
- Support for TE0820 Modules in Vitis 2023.2, AI 3.5 SW, AI 3.0 DPUCZDX8G (2024) Download [2024] :
- Support for TE0821 Modules in Vitis 2023.2, AI 3.5 SW, AI 3.0 DPUCZDX8G (2024) Download [2024] :
- Support for STM32H573I DK V1.4.0 web server (2024) Download [2024] :
- Adaptive Lattice Filter on STM32H7 Devices (2024) Download [2024] :
- Support for TE0821 modules with Vitis AI 3.0 DPU (2024) Download [2024] :
- Support for TE0820 modules with Vitis AI 3.0 DPU (2024) Download [2024] :
- Support for STM32H573I-DK web server (2024) Download [2024] :
- Compilation of Vitis AI 3.0 models for different configurations of AMD DPUs. (2024) Download [2024] :
- Support for TE0802-02-2AEV2-A board with Vitis AI 3.0 DPU and VGA display (2024) Download [2024] :
- Support for TE0802-02-1BEV2-A board with Vitis AI 3.0 DPU and VGA display (2024) Download [2024] :
- Hand detection ultrasound based application implemented on the FPGA platform, Book of abstracts. 6th International Caparica Conference on Ultrasonic-based applications from analysis to synthesis, p. 107-107 [2023] :
- Xilinx Vitis AI facedetect and resnet50 Demo on Trenz Electronic TE0802 02 with ZU2CG and 1 GB LPDD4 (2023) Download [2023] :
- Xilinx Vitis AI facedetect Demo on Trenz Electronic TE0820 4EV SoM with TE0701 06 Carrier Board and Avnet HDMI In/Out FMC Card (2023) Download [2023] :
- Xilinx Vitis AI 'facedetect' Demo on Trenz Electronic board TE0808 SoM + TEBF0808 Carrier (2022) Download [2022] :
- All VART Examples from Xilinx Vitis AI 2.0 for Trenz Electronic board TE0808 SoM + TEBF0808 Carrier (2022) Download [2022] :
- Testing all Samples from Xilinx Vitis AI Library 2.0 on Trenz Electronic board TE0808 SoM + TEBF0808 Carrier (2022) Download [2022] :
- Xilinx Vitis AI ‘facedetect’ and ‘resnet50’ Demo on Trenz Electronic TE0821-01-2cg-4GB SoM + TE0706-3 Carrier (2022) Download [2022] :
- STM32H753 Terminal with Zynq Ultrascale+ Accelerator (2021) Download [2021] :
- STM32H753 Terminal with TE0723 03 07S 1C Accelerator HW Data Movers (2021) Download [2021] :
- Data Movers in DTRiMC tool for TE0726 03M 07S board (2021) Download [2021] :
- Eight FP03x8 accelerators for TE0808-09-EG-ES1 module on TEBF0808 carrier board (2021) Download [2021] :
- DTRiMC tool for TE0820-03-4EV-1E module on TE0701-06 carrier board (2021) Download [2021] :
- DTRiMC tool for TE0820-02-3CG-1E module on TE0701-06 carrier board (2021) Download [2021] :
- DTRiMC tool for TE0808-15-EG-1EE module on TEBF0808 carrier board (2021) Download [2021] :
- DTRiMC tool for TE0726-03M board (2021) Download [2021] :
- DTRiMC tool for TE0808-09-EG-ES1 module on TEBF0808 carrier board (2021) Download [2021] :
- Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project, Proceedings - Euromicro Conference on Digital System Design, DSD 2020, p. 378-385, Eds: Trost A., Zemva A., Skavhaug A. Download DOI: 10.1109/DSD51259.2020.00067 [2020] :
- Trenz TEBF0808 + TE0808 04 6EB21A SoM with Analog Devices AD FMCDAQ2 EBZ Evaluation Board (2019) Download [2019] :
- Evaluation version of 8xSIMD FP01x8 accelerator for ArduZynq shield (2019) Download [2019] :
- Industrial 40 nm Demonstrator NUCLEO STM32H755ZI-Q (2019) Download [2019] :
- Benchmarks for STM32H7 MCUs (2019) Download [2019] :
- FP01x8 Accelerator on TE0726-03M (2019) Download [2019] :
- Two serial connected evaluation versions of FP03x8 accelerators for TE0820-03-4EV-1E module on TE0701-06 carrier board. (2019) Download [2019] :
- Video Input/Output IP Cores for Xilinx ZCU102 with Avnet HDMI Input/Output FMC Module (2019) Download [2019] :
- Video Input/Output IP Cores for TE0820 SoM with TE0701 Carrier and and Avnet HDMI Input/Output FMC Module (2019) Download [2019] :
- Design Time and Run Time Resources for Zynq Ultrascale+ TE0820-03-4EV-1E with SDSoC 2018.2 Support (2019) Download [2019] :
- Design Time and Run Time Resources for Zynq Ultrascale+ TE0808-04-15EG-1EE with SDSoC 2018.2 Support (2019) Download [2019] :
- Design Time and Run Time Resources for the ZynqBerry Board TE0726-03M with SDSoC 2018.2 Support (2019) Download [2019] :
- The FitOptiVis ECSEL project: highly efficient distributed embedded image/video processing in cyber-physical systems, Proceedings of the 16th ACM International Conference on Computing Frontiers, p. 333-338, Eds: Palumbo F., Becchi M., Schulz M., Sato K. Download DOI: 10.1145/3310273.3323437 [2019] :
- Arrowhead Compatible Zynq Ultrascale+ Systems with Xilinx SDSoC 2018.2 Support (2019) Download [2019] :
- Arrowhead client on Zynq 7000 device with support for the Xilinx SDSoC 2018.2 HW accelerators (2019) Download [2019] :
- Arrowhead Compatible Zynq with SDSoC 2017.4 and Floating-Point 8xSIMD EdkDSP Accelerators (2019) Download [2019] :
- Live Canny Edge Detection (2018) Download [2018] :
- Stereo Demo (2018) Download [2018] :
- Noise Cancellation Using QRD RLS Algorithms (2018) Download [2018] :
- Compact Zynq System 2017.4 with SW-defined Floating-Point 8xSIMD EdkDSP Accelerator (2018) Download [2018] :
- Compact Zynq System with SW-defined Floating-Point 8xSIMD EdkDSP Accelerator (2018) Download [2018] :
- SW Defined Floating Point 8xSIMD EdkDSP IP Serving for Adaptive Noise Cancellation (2018) Download [2018] :
- Video Processing Demonstrator with Full HD Sensor and 8xSIMD EdkDSP Accelerator IP Core (2018) Download [2018] :
- Camera-to-touchscreen design, Proceedings of 6th International Workshop on Mathematical Models and their Applications (IWMMA’2017), p. 94-99 Download [2017] :
- Adaptive RLS Algorithms Reference Implementations (2017) Download [2017] :
- A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC2, Computer Safety, Reliability, and Security : SAFECOMP 2017 Workshops, ASSURE, DECSoS, SASSUR, TELERISE, and TIPS, p. 127-140, Eds: Tonetta Stefano, Schoitsch Erwin, Bitsch Friedemann Download DOI: 10.1007/978-3-319-66284-8 [2017] :
- Full HD Video Processing in HW with three EdkDSP 8xSIMD Accelerators for TE0715-30-1 SoM on TE0701-06 Carrier (2017) Download [2017] :
- Full HD Video Processing in HW with three EdkDSP 8xSIMD Accelerators for TE0715-04-30-3E SoM on TE0701-06 Carrier (2017) Download [2017] :
- Full HD Video Processing in HW with three EdkDSP 8xSIMD Accelerators for TE0715-30-1 SoM on EMC2-DP-V2 Carrier (2017) Download [2017] :
- Informační den: Informační a komunikační technologie v programu Horizont 2020 Download [2016] :
- Asymmetric Multiprocessing with MicroBlaze, EdkDSP Accelerator and Toshiba Sensor Video for Automotive grade Zynq on TE0720-03-1QF SoM on TE0701-05 Carrier (2016) Download [2016] :
- Asymmetric Multiprocessing with MicroBlaze, EdkDSP Accelerator and Toshiba Sensor Video Processing for low cost Zynq on TE0720-03-1CF SoM on TE0701-05 Carrier (2016) Download [2016] :
- EMC2-DP HDMI in HDMI out Platform (2016) Download [2016] :
- Full HD HDMI In-Out HW-Accelerated Demos for Zynq System-on-Module TE0715-03-30-1I and Sundance EMC2-DP-V2 Platform (2016) Download [2016] :
- SDSoC 2015.4 Standalone BSP with Full HD HDMI In-Out SW and HW Demos for Automotive Zynq TE0720-03-1QF Module or Commercial Zynq TE0720-03-1CF Module on TE0701-05 Carrier Board (2016) Download [2016] :
- SDSoC 2015.4 Standalone BSP with Full HD HDMI In-Out SW and HW Demos for Zynq System-on-Module TE0720-03-2IF and TE0701-05 Carrier Board (2016) Download [2016] :
- SDSoC 2015.4 Standalone BSP with Full HD HDMI In-Out with SW and HW Demos for Zynq System-on-Module TE0715-03-30 and Sundance EMC2-DP-V2 Platform (2016) Download [2016] :
- ALMARVI Python Camera Platform (2016) Download [2016] :
- Python 1300 Sensor Video Processing in HW with EdkDSP 8xSIMD Accelerator for TE0720-03-2IF SoM on TE0701-05 Carrier (2016) Download [2016] :
- Full HD HDMI In-Out HW-Accelerated Demos for Zynq System-on-Module TE0720-03-2IF and TE0701-05 Carrier Board (2016) Download [2016] :
- Zynq Platform with UTIA EdkDSP Accelerator and Toshiba Sensor Video Processing in HW for TE0720-03-2IF SoM on TE0701-05 Carrier (2016) Download [2016] :
- Full HD Toshiba Video Sensor Platform with Automotive Grade Arm Zynq on TE0720-03-1QF SoM on TE0701-05 Carrier (2016) Download [2016] :
- Toshiba Video Sensor Evaluation Platform for TE0720-03-2IF SoM on TE0701-05 Carrier (2016) Download [2016] :
- Python 1300 Video Sensor Evaluation Platform for TE0720-03-2IF SoM on TE0701-05 Carrier (2016) Download [2016] :
- Camera to Touchscreen Demonstration for MicroZed 7020 carrier board, Avnet 7-inch Zed Touch Display and Avnet Toshiba Industrial 1080P60 Camera Module (2016) Download [2016] :
- EdkDSP Accelerator IP Evaluation in Vivado 2014.4 Artix7 AC701 board (2015) Download [2015] :
- Evaluation of Asymmetric Multiprocessing for Zynq System-on-Modules TE0720-02-2IF, TE0720-02-1CF, TE0720-02-1QF with Carrier Board TE0701-05 (2015) Download [2015] :
- Information and communication technologies in Horizon 2020 Download [2015] :
- Video Chain Demonstrator on Xilinx Kintex7 FPGA with EdkDSP Floating Point Accelerators, Proceedings 2015 International Conference on Embedded Computer Systems: Architectures, Modelling and Simulation (SAMOS XV), Eds: Soudris Dimitrios, Carro Luigi DOI: 10.1109/SAMOS.2015.7363690 [2015] :
- Video Input/Output Demonstration for Trenz TE0701-05, TE0720-02-1CF, TE0720-02-1QF, TE0720-02-2IF and Avnet HDMI Input/Output FMC Module (2015) Download [2015] :
- Informační a komunikační technologie v programu Horizont 2020 Download [2015] :
- Computation and Communication Blocks for Xilinx Kintex7 FPGA with UTIA EdkDSP Accelerators. Vivado 2013.4 Designs with SW Demos (2014) Download [2014] :
- UTIA EdkDSP Demonstrator in Xilinx 3S700AN FPGA with Embedded FLASH and NV RAM (2014) Download [2014] :
- Asymmetric Multiprocessing on ZYNQ ZC702 board with EdkDSP Accelerators for Xilinx Vivado 2013.4 Design Flow (2014) Download [2014] :
- Internet of Things Building Blocks for Xilinx Artix7 FPGA with UTIA EdkDSP Accelerators. Vivado 2013.4 Designs with SW Demos (2014) Download [2014] :
- Asymmetric Multiprocessing (AMP) on ZYNQ with EdkDSP Accelerators on Xilinx ZC702 Board - ISE 14.5 (2014) Download [2014] :
- UTIA EdkDSP Platform Demonstrator on Xilinx SP605 Board – PLB Bus (2014) Download [2014] :
- Setkání zástupců v oblasti ICT v ČR a seznámení s draftem pracovního programu pro oblast ICT v H2020 [2013] :
- EDKDSP: Reprogrammable Floating Point Accelerators on KINTEX FPGA with HDMI, 2013 Design, Automation and Test in Europe Download [2013] :
- ARTEMIS Brokerage Event Call 2012 Download [2012] :
- In-circuit, Run-time Compiler of Finite State Machines for the UTIA EdkDSP Customizable Accelerators, Fourth Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, p. 32-33, Eds: Silvano Cristina, Agosta Giovanni, Cardoso Joao Download [2012] :
- Dynamic Placement Applications into Self Adaptive Network on FPGA, 2011 IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS 2011), p. 453-456, Eds: Vierhaus Heinrich T. , Pawlak Adam, Schölzel Mario, Steininger Andreas, Kraemer Rolf, Raik Jaan Download DOI: 10.1109/DDECS.2011.5783135 [2011] :
- Účast ČR ve společných technologických iniciativách ARTEMIS a ENIAC, Hovory s informatiky, p. 95-113, Eds: Klímová H., Kuželová D., Šíma J., Wiedermann J., Žák S. Download [2011] :
- Český národní informační den společných technologických iniciativ ARTEMIS a ENIAC [2011] :
- Funkční vzorek systému pro vizualizaci funkce a ovládání vzdáleného HW s VLAM periferními moduly (2011) [2011] :
- NOR FLASH Core – Funkční vzorek řadiče paměti Intel StrataFlash (2011) [2011] :
- SPI FLASH Core – Funkční vzorek řadiče paměti SPI Serial Flash (2011) [2011] :
- AD Core – Funkční vzorek řadiče A/D převodníku se sběrnicí SPI (2011) [2011] :
- BASIC IO CORE – Funkční vzorek řadiče elektronického potenciometru (2011) [2011] :
- DA Core - Funkční vzorek řadiče D/A převodníku se sběrnicí SPI (2011) [2011] :
- PWM Core - funkční vzorek generátoru pulzně šířkové modulace (2011) [2011] :
- FG Core - funkční vzorek generátoru kmitočtu (2011) [2011] :
- FC Core - funkční vzorek čítače frekvence (2011) [2011] :
- LCD Core - Funkční vzorek řadiče LCD displeje (2011) [2011] :
- Floating Point Accelerator Families bce_fp01_1x1_0_plbw_v1_|10|20|30|_a bce_fp01_1x2_0_plbw_v1_|10|20|30|40|_a for Xilinx Spartan3 DSP 1800 Board and Petalogix Petalinux-v0.40-final (2009) [2009] :
- Demonstrator of Floating Point Accelerators bce_fp01_1x1_0_plbw_v1_1|10|20|30_a Kit: Xilinx Spartan-3AN OS: petalinux-v0.40-final (2009) [2009] :
- Proceedings 19th International Conference on Field Programmable Logic and Applications (FPL), ÚTIA AV ČR, IEEE (Praha, New York, 2009) [2009] :
- ARTEMIS / ENIAC Joint Undertaking - Seminář ke 2. výzvě [2009] :
- PicoBlaze lekce 4: Aplikace pro výuku asembleru procesoru PicoBlaze (2008) [2008] :
- Řadiče periferií pro vývojovou desku Spartan3E Starter Kit (2008) [2008] :
- Adaptive Noise Canceller Migration Demo (2008) [2008] :
- Workshop on Embedded Systems Education and Training [2008] :
- Increasing the Level of Abstraction in FPGA-based Designes, International Conference on Field Programmable Logic and Applications, p. 5-10 Download [2008] :
- Design Flow for Reconfigurable MicroBlaze Accelerators, 4th International Workshop on Reconfigurable Communication Centric System-on-Chips Workshop Proceedings, p. 133-140, Eds: Moreno Manuel J., Madrenas Jordi, Sassatelli Gilles, Hübner Michael, Zipf Peter [2008] :
- Proposed architecture of configurable, adaptable SoC, The IET Irish Signals and Systems Conference ISSC 2008, p. 368-373, Eds: Morgan Fearghal, Glavin Martin, Jones Edward [2008] :
- ARTEMIS / ENIAC Joint Undertaking Information event [2008] :
- Embedded Development Environment for a Family of Xilinx FPGA, Regional Conference on Embedded and Ambient Systems Book of Abstracts, p. 16-16, Eds: Varga Antila K., Kiss Ákos, Marsiske Stefan, Vásárhelyi József [2007] :
- Preparation ARTEMIS and the Czech republic: current status and related issues, Regional Conference on Embedded and Ambient Systems Book of Abstracts, p. 15-15, Eds: Varga Antila K., Kiss Ákos, Marsiske Stefan, Vásárhelyi József [2007] :
- Adaptive Noise Canceller Demo based on the LS Lattice Filter (2007) Download [2007] :
- Modelling Self-Adaptive Networked Entities in Matlab/Simulink, Technical Computing Prague 2007, p. 1-8 [2007] :
- Simulation of MCU hardware peripherals, Technical Computing Prague 2007, p. 1-7 [2007] :
- Accelerating MicroBlaze Floating Point Operations, Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL), p. 621-624, Eds: Bertels Koen, Najjar Walid, Genderen Arjan, Vassiliadis Stamatis [2007] :
- PicoBlaze lekce 3: sériová komunikace RS232 a testování IP jader pomocí procesoru PicoBlaze, ÚTIA AV ČR (Praha, 2007) [2007] :
- PicoBlaze lekce 2: generování VHDL a implementace systému s procesorem PicoBlaze do FPGA v prostředí Xilinx ISE, ÚTIA AV ČR (Praha, 2007) [2007] :
- PicoBlaze lekce 1: assembler, C překladač a simulační prostředí, ÚTIA AV ČR (Praha, 2007) [2007] :
- Identifikace limitací dosavadních technologií v kontextu projektu VLAM, ÚTIA AV ČR (Praha, 2007) [2007] :
- RLS Lattice Demo, ÚTIA AV ČR (Praha, 2006) [2006] :
- Přechod ústavů Akademie věd na V.V.I . a jeho dopad na běžící projekty 6.RP EU [2006] :
- Robotics in IST FP7 [2006] :
- Hardware co-simulation with communication server from MATLAB/Simulink, Technical computing Prague 2006. 14th annual conference proceedings, p. 13-20 [2006] :
- Design and verification methodology for reconfigurable designs in Atmel FPSLIC, Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits adn Systems, p. 79-80, Eds: Reorda M. S., Novák O., Straube B. [2006] :
- GIN - notetaker for blind people: An example of using dynamic reconfiguration of FPGAs, ACACES 2005. Advanced Computer Architecture and Compilation for Embedded Systems, p. 15-18, HiPEAC Network of Excellence (Ghent, 2005) [2005] :
- Výměna zkušeností řešitelů evropských projektů po 1. kole auditů 6. RPEU [2005] :
- Performance tuning of interative algorithms in signal processing, Proseedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005, p. 699-702, Eds: Rissa T., Wilton S., Leong P. [2005] :
- Scalable Floating Point Simulation Package float-dk-rel2. (Program), ÚTIA AV ČR (Praha, 2005) [2005] :
- Double Precision Simulation Package double-dk-rel2. (Program), ÚTIA AV ČR (Praha, 2005) [2005] :
- Floating point controller as a picoblaze network on a single spartan 3 FPGA, MAPLD 2005 International Conference Proceeding, p. 1-11 [2005] :
- Reconfigurable floating point co-processor for atmel FPSLIC, MAPLD 2005 International Conference Proceedings, p. 1-12 [2005] :
- Reconfigurable Scrolling Demo, ÚTIA AV ČR (Praha, 2004) [2004] :
- Reconfigurable 24-Bit Floating-Point Coprocessor Demo, ÚTIA AV ČR (Praha, 2004) [2004] :
- Workshop FET. Future and Emerging Technologies in the frame of IST FP6 [2004] :
- Reconfigurable system-on-a-programmable-chip platform, Proceedings of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, p. 21-28 [2004] :
- Prototyping Board for CAK. (Program), ÚTIA AV ČR (Praha, 2003) [2003] :
- An Introduction to the Xilinx System Generator. (Program), ÚTIA AV ČR (Praha, 2003) [2003] :
- European Logarithmic Microprocessor. (Program), ÚTIA AV ČR (Praha, 2003) [2003] :
- Lattice IP Core used in Real-time Lattice Demo on XESS Board. (Program), ÚTIA AV ČR (Praha, 2003) [2003] :
- RLS Lattice - Celoxica RC200 Demo. (Program), ÚTIA AV ČR (Praha, 2003) [2003] :
- Dynamic reconfiguration of Atmel FPGAs, UK ACM SIGDA 3rd Workshop on Electronic Design Automation, p. 1-4, University of Southampton (Southampton, 2003) [2003] :
- Dynamic reconfiguration of FPGAs, Recent Trends in Multimedia Information Processing. Proceedings, p. 288-291, Eds: Šimák B., Zahradník P., Czech Technical University (Prague, 2003) [2003] :
- Using logarithmic arithmetic for FPGA implementation of the Givens rotations, Proceedings of the Sixth Baiona Workshop on Signal Processing in Communications, p. 199-204, Eds: Mosquera C., Perez-Gonzales F., Universidade de Vigo (Vigo, 2003) [2003] :
- FPGA implementation of the adaptive lattice filter, Field-Programmable Logic and Applications. Proceedings of the 13th International Conference, p. 1095-1098, Eds: Cheung P. Y. K., Constantinides G. A., de Sousa J. D., Springer (Berlin, 2003) [2003] :
- Dynamic runtime partial reconfiguration in FPGA, ECMS 2003. 6th International Workshop on Electronics, Control, Measurement and Signals, p. 294-298, Eds: Nouza J., Drábková J., Technical University (Liberec, 2003) [2003] :
- Lattice adaptive filter implementation for FPGA, FPGA 2003 ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, p. 246, ACM (Monterey, 2003) [2003] :
- Ideal-ist Conference Information Society Technology in the 6th Framework Programme (2002) [2002] :
- e-2002 e-Work & e-Business Conference (2002) [2002] :
- Logarithmic Arithmetic for Real Data Types and Support for MATLAB/SIMULINK Based Rapid-FPGA-Prototyping, ÚTIA AV ČR (Praha, 2002) [2002] :
- The Gauss-Seidel Fast Affine Projection algorithm, IEEE Workshop on Signal Processing Systems. Proceedings, p. 109-114, Eds: Parhi K., Shanbhag N., IEEE (San Diego, 2002) [2002] :
- Analysis of the LNS implementation of the fast affline projection algorithms, Proceedings of the Irish Signals and Systems Conference 2002. ISSC 2002, p. 251-255, Eds: Marnane W., Lightbody G., Pesch D., Institute of Technology (Cork, 2002) [2002] :
- Pipelined implementations of the A Priory Error-Feedback LSL algorithm using logarithmic arithmetic, Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, p. 2681-2684, IEEE (Orlando, 2002) [2002] :
- Logarithmic number system and floating-point arithmetics on FPGA, Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, p. 627-636, Eds: Glesner M., Zipf P., Renovell M., Springer (Berlin, 2002) [2002] :
- Matlab Toolbox for high-level bit-exact emulation of HandelC VHDL FPGA designs, Design, Automation and Test in Europe DATE˙02, p. 264, Eds: Sciuto D., Kloos C. D., IEEE (Los Alamitos, 2002) [2002] :
- Logarithmic arithmetic core based RLS LATTICE implementation, Design, Automation and Test in Europe DATE 02, p. 271, Eds: Sciuto D., Kloos C. D., IEEE (Los Alamitos, 2002) [2002] :
- Ideal-ist Workshop European IT Research Programme (IST) Successful Proposal Writing (2001) [2001] :
- Opportunities in the European Union's IST Programme (2001) [2001] :
- Ideal-ist Workshop European IT Research Programme (IST) Successful Proposal Writing (2001) [2001] :
- Managing EC Research Project - Workshop and Brokerage (2001) [2001] :
- RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic, ÚTIA AV ČR (Praha, 2001) [2001] :
- 32-bit Logarithmic ALU for Handel-C 2.1 and Celoxica DK1, ÚTIA AV ČR (Praha, 2001) [2001] :
- Pipelined Logarithmic 32bit ALU for Celoxica DK1, ÚTIA AV ČR (Praha, 2001) [2001] :
- The European Logarithmic Microprocessor - a QRD RLS Applications, ÚTIA AV ČR (Praha, 2001) [2001] :
- A Comparison of FPGA Implementation of the A Priori Error-Feedback LSL Algorithm using Logarithmic Arithmetic, ÚTIA AV ČR (Praha, 2001) [2001] :
- Implementation of Normalized RLS Lattice on Virtex, ÚTIA AV ČR (Praha, 2001) [2001] :
- Extended Precision Logarithmic Arithmetic, Signal Systems and Computers 2000, 34th Asilomar Conference on Signal Systems and Computers. Proceedings, p. 124-129, IEEE Signal Processing Society (Monterey, 2001) [2001] :
- Implementing Advanced Equalization Algorithms using Simulink with Embedded Alpha AXP Coprocessor, ÚTIA AV ČR (Praha, 2001) [2001] :
- Pipelined logarithmic 32bit ALU for Celoxica DK1, Sborník příspěvků 9.ročníku konference MATLAB 2001, p. 72-80, Eds: Procházka A., Uhlíř J., VŠCHT (Praha, 2001) [2001] :
- Extended Precision LNS Arithmetic, ÚTIA AV ČR (Praha, 2001) [2001] :
- FPGA Implementation of Logarithmic Unit Core, ÚTIA AV ČR (Praha, 2001) [2001] :
- Logarithmic ALU 32-bit for Handel C 2.1 and Celoxica DK1, Celoxica User Conference. Proceedings, Celoxica (Abington, 2001) Download [2001] :
- Implementation of Error-Feedback RLS Lattice on Virtex using logarithmic arithmetic, Advances in Systems Science: Measurement, Circuits and Control. Proceedings, p. 517-521, Eds: Mastorakis N. E., Pecorelli-Peres L. A., WSES Press (Rethymno, 2001) [2001] :
- Review and Classification of RLS Array Algorithms for LNS Arithmetics, ÚTIA AV ČR (Praha, 2001) [2001] :
- FPGA implementation of logarithmic unit core, Embedded Intelligence 2001, p. 547-554, Design & Elektronik (Nürnberg, 2001) [2001] :
- Implementation of (Normalised) RLS Lattice on Virtex, Field-Programmable Logic and Applications. Proceedings, p. 91-100, Eds: Brebner G., Woods R., Springer (Berlin, 2001) [2001] :
- Structure estimation for systems described by radial basis functions based on normalized QR filtering, Preprints of the 1st IFAC/IEEE Symposium on System Structure and Control, IFAC (Prague, 2001) [2001] :
- Arithmetic on the European Logarithmic Microprocessor, ÚTIA AV ČR (Praha, 2001) [2001] :
- Implementing advanced equalization algorithms using Simulink with embedded Alpha AXP coprocessor, Fifth IMA International Conference on Mathematics in Signal Processing, p. 11-14, University of Warwick (Warwick, 2000) [2000] :
- Simulation of RLS and LMS algorithms for adaptive noise cancellation in MATLAB, Sborník příspěvků 8. ročníku konference MATLAB 2000, p. 301-305, VŠCHT (Praha, 2000) [2000] :
- FPGA implementation of logarithmic unit, Sborník příspěvků 8. ročníku konference MATLAB 2000, p. 84-90, VŠCHT (Praha, 2000) [2000] :
- Vstup českých institucí do evropské informační společnosti, Česko-slovenská konference RUFIS 2000, p. 27-32, VUT (Brno, 2000) [2000] :
- A toolbox for model-based fault detection and isolation, European Control Conference. ECC '99, VDI/VDE GMA (Karlsruhe, 1999) Download Download [1999] :
- Generation of Simulink S-functions, ÚTIA AV ČR (Praha, 1999) [1999] :
- Konference k zahájení 5. rámcového programu Evropské unie, MŠMT (Praha, 1999) [1999] :
- Informační den k programu IST, Technologické centrum AV ČR (Praha, 1999) [1999] :
- Port of Pascal FPGA-logarithmic-unit simulator to Simulink/RTW, Sborník příspěvků 7. ročníku konference MATLAB '99, p. 84-90, VŠCHT (Praha, 1999) [1999] :
- RTW support for parallel 64-bit Alpha AXP-based platforms, Sborník příspěvků 7. ročníku konference MATLAB '99, p. 238-244, VŠCHT (Praha, 1999) [1999] :
- RTW support for low cost C31 board, Sborník příspěvků 7. ročníku konference MATLAB '99, p. 231-237, VŠCHT (Praha, 1999) [1999] :
- Quasi-Bayes estimation applied to normal mixture, Preprints of the 3rd European IEEE Workshop on Computer-Intensive Methods in Control and Data Processing, p. 77-82, Eds: Rojíček J., Valečková M., Kárný M., Warwick K., ÚTIA AV ČR (Praha, 1998) Download [1998] :
- Robust adaptive controller with fine grain parallelism, Preprints of the IFAC Workshop on Adaptive Systems in Control and Signal Processing, p. 436-441, IFAC (Glasgow, 1998) Download [1998] :
- Acceleration of computation-intensive algorithms on parallel Alpha AXP processors, Preprints of the 3rd European IEEE Workshop on Computer-Intensive Methods in Control and Data Processing, p. 89-98, Eds: Rojíček J., Valečková M., Kárný M., Warwick K., ÚTIA AV ČR (Praha, 1998) Download [1998] :
- Numerical Analysis of a Normalized QR Filter Using Probability Description of Propagated Data, ÚTIA AV ČR (Praha, 1998) [1998] :
- HSLA 3D Monitor Package, ÚTIA AV ČR (Praha, 1998) [1998] :
- HSLA DSP Package, ÚTIA AV ČR (Praha, 1998) [1998] :
- Results of the Global Probability Analysis Approach, ÚTIA AV ČR (Praha, 1998) [1998] :
- Rapid prototyping of adaptive control algorithms on parallel multiprocessors, Signal Processing Symposium, p. 115-118, IEEE (Leuven, 1998) Download [1998] :
- Rapid prototyping and parallel processing under MATLAB 5, MATLAB Conference 1997, p. 120-125, Kimhua Technology (Seoul, 1997) [1997] :
- Parallel processing on Alphas under MATLAB 5, SOFSEM '97: Theory and Practice of Informatics, p. 440-448, Eds: Plášil F., Jeffery K. G., Springer (Berlin, 1997) [1997] :
- Para-Mat parallel processing under MATLAB, Simulationstechnik. Tagungsband, p. 684-687, Eds: Kuhn A., Wenzel S., Vieweg (Braunschweig, 1997) [1997] :
- Rapid prototyping and parallel processing under MATLAB 5, Tagungsband. 3. Zittauer Workshop Magnetlagertechnik, p. 101-104, Eds: Hampel R., Worlitz F., IPM (Zittau, 1997) Download [1997] :
- Extension of MATLAB parallel accelerator, Computer-Intensive Methods in Control and Signal Processing. Preprints of the 2nd European IEEE Workshop CMP'96, p. 155-160, Eds: Berec L., Rojíček J., Kárný M., Warwick K., ÚTIA AV ČR (Praha, 1996) [1996] :
- Alpha Bridge - high performance computing with MATLAB, Industrial Applications of MATLAB and Simulink for the Analysis of Electro- and Hydro- Mechanical Systems. Preprints, p. 11-16, Matlab UG (Birmingham, 1995) Download [1995] :
- The block regularised parameter estimator and its parallelisation, Identification and Optimization, Oriented for Use in Adaptive Control. Preprints, p. 107-120, Eds: Böhm J., Rojíček J., ÚTIA AV ČR (Praha, 1995) [1995] :
- Normalised Givens rotations for recursive least squares processing, VLSI Signal Processing, VIII, p. 313-322, Eds: Nishitani T., Parhi K., IEEE (New York, 1995) [1995] :
- [Recenze], Automatica 31 10 (1995), p. 1519-1521 [1995] :
- Alpha-Bridge for MATLAB 4, Transputer Applications and Systems '95. Proceedings, p. 175-189, Eds: Cook B. M., Nixon P., IOS Press (Harrogate, 1995) [1995] :
- Identification with directional parameter tracking for high-performance fixed-point implementations, The Sixth Irish DSP and Control Colloquium, p. 215-222, Eds: Gaston F., Dodds G., Techman (Belfast, 1995) Download [1995] :
- Numerical analysis of normalized RLS filter using a probability description of propagated data, Algorithms and Parallel VLSI Architectures III, p. 61-72, Eds: Moonen M., Catthor F., Elsevier (Amsterdam, 1994) [1994] :
- [Recenze], Automatica 30 5 (1994), p. 917-918 [1994] :
- Direct software bridge MATLAB-transputer boards, Signal Processing Conference. Proceedings, p. 1601-1604, EUSIPCO (Edinburgh, 1994) [1994] :
- Numerical analysis of normalized RGS filter by probability description of propagated data. Abstract, Algorithms and Parallel VLSI Architectures. Abstracts, p. -, Katholieke Universiteit (Leuven, 1994) [1994] :
- The block regularized linear quadratic optimal controller, IEE International Conference on Control '94, p. 1254-1259, IEE (London, 1994) Download [1994] :
- Systolic arrays for identification of systems with variable structure, Computer-Intensive Methods in Control and Signal Processing, p. 123-132, Eds: Kulhavá L., Kárný M., Warwick K., ÚTIA AV ČR (Praha, 1994) [1994] :
- Parallel Normalized Identification Algorithm with Lattice Feedback Regularization, ÚTIA AV ČR (Praha, 1994) [1994] :
- Direct Software Bridge MATLAB-Transputer Boards, ÚTIA AV ČR (Praha, 1994) [1994] :
- Numerical Analysis of a Normalized RLS Filter Using a Probability Description of Propagated Data, ÚTIA AV ČR (Praha, 1994) [1994] :
- Systolic Arrays for Identification of Systems with Variable Structure, ÚTIA AV ČR (Praha, 1994) [1994] :
- Lattice feedback regularised identification, 10th IFAC Symposium on System Identification. Preprints, p. 277-282, Eds: Blanke M., Söderström T., IFAC (Copenhagen, 1994) [1994] :
- Matlab transputer bridge. Abstract, 10th IFAC Symposium on System Identification. Preprints, p. 31, Eds: Blanke M., Söderström T., IFAC (Copenhagen, 1994) [1994] :
- The Block Regularised Linear Quadratic Optimal Controller, ÚTIA AV ČR (Praha, 1994) [1994] :
- Transputer Implementation of Block Regularised Filtering, ÚTIA AV ČR (Praha, 1994) [1994] :
- Structure Determination and Tracking for Parallel Radial Basic Function Based Nonlinear Networks, ÚTIA AV ČR (Praha, 1994) [1994] :
- Lattice Feedback Regularised Identification, ÚTIA AV ČR (Praha, 1994) [1994] :
- The Cell-Level Description of Systolic Block Regularised QR Filter., ÚTIA AV ČR (Praha, 1994) [1994] :
- The Block Regularised Parameter Estimator and Its Parallel Implementation, ÚTIA AV ČR (Praha, 1994) [1994] :
- Regularised Lattice-Ladder Adaptive Filter, ÚTIA AV ČR (Praha, 1994) [1994] :
- Regularised Lattice-Ladder Adaptive Filter, Mutual Impact of Computing Power and Control Theory, p. 245-257, Eds: Kárný M., Warwick K., Plenum Press (New York, 1993) [1993] :
- Structure Determination and Tracking for Parallel Radial Basis Function Based Nonlinear Networks, Innovative Approaches to Modelling and Optimal Control of Large Scale Pipeline Networks, p. 75-84, ÚTIA AV ČR (Prague, 1993) [1993] :
- The Cell Level Description of Systolic Block Regularised QR Filter, VLSI Signal Processing, p. 298-306, Eds: Eggermont L. D. J., Dewilde P., IEEE (New York, 1993) [1993] :
- Transputer Implementation of Block Regularised Filtering, Progress in Transputer Computing Technology, p. 1-15, Eds: Kulhavá L., Schier J., Kárný M., ÚTIA AV ČR (Prague, 1993) [1993] :
- A Nonlinear Systolic Filter with Radial Basis Function Estimation, Neural Computing Research and Applications, p. 183-190, IOP Publ. (London, 1993) [1993] :
- The Lattice-Ladder with Generalized Forgetting, Linear Algebra for Large Scale and Real-Time Applications, p. 397-398, Eds: Moonen M. S., Golub G. H., De Moor B. L. R., Kluwer Academic (Leuven, 1993) [1993] :
- Parallel Implementation of Restricted Parameter Tracking, Queen's University (Belfast, 1993) [1993] :
- Fast Ladder-Lattice Identification Architecture with Numerically Robust Tracking of Parameters, Algorithms and Architectures for Real-Time Control, p. 105-111, Eds: Fleming P. O., Jones D. I., Pergamon Press (Oxford, 1992) [1992] :
- Systolic Implementation of the Regularized Parameter Estimator, VLSI Signal Processing 6, p. 520-529, Eds: Yao K., Jain R., Przytula W., Rabaey J., IEEE (New York, 1992) [1992] :
- Unified Design of Fast Array Estimators, Queen's University (Belfast, 1992) [1992] :
- Parallel Implementation of Restricted Parameter Tracking, Mathematics in Signal Processing, p. 86-88, University of Warwick (SouthendonSea, 1992) [1992] :
- Regularised Lattice-Ladder Adaptive Filter, IFAC Workshop on Mutual Impact of Computing Power and Control Theory. MICC '92, p. 143-150, Eds: Kárný M., Warwick K., ÚTIA ČSAV (Prague, 1992) [1992] :
- Tools for Implementation of Parallel Algorithms for Adaptive Control and Signal Processing, 4th IFAC International Symposium on Adaptive Systems in Control and Signal Processing. ACASP '92, p. 727-730, Eds: Landau I. D., Dugard L., M'Saad M., Laboratoire d'Automatique (Grenoble, 1992) [1992] :
- A Joint Criterion for Exponential Directional and Mixed Parameter Tracking, 4th IFAC International Symposium on Adaptive Systems in Control and Signal Processing. ACASP '92, p. 687-692, Eds: Landau I. D., Dugard L., M'Saad M., Laboratoire d'Automatique (Grenoble, 1992) [1992] :
- Neural Nets for System Applications, IEE/ÚTIA (Praha, 1991) [1991] :
- Identification Algorithms for Parallel Computing Networks with Fixed Point Arithmetic, Neural Nets for System Applications, p. -, IEE/ÚTIA (Prague, 1991) [1991] :
- Fast and Adaptive Identification Algorithms Suitable for Neural Network Applications, Neural Nets for System Applications, p. -, IEE/ÚTIA (Prague, 1991) [1991] :
- A Recursive Modified Gram-Schmidt Identification with Directional Tracking of Parameters, Preprints of the 9th IFAC/IFORS Symposium on Identification and System Parameter Estimation, p. 1707-1712, AKA PRINT Nyomdaipari (Budapest, 1991) [1991] :
- Terminály pro zrakově postižené, ÚTIA ČSAV (Praha, 1990) [1990] :
- Bayesian Analysis of System Parameter Variations, Based on Testing of Hypotheses about Forgetting Factors, RuhrUniversität (Bochum, 1989) [1989] :
- Bayesian Recursive Identification of Large Scale Interconnected Stochastic Time Variable Systems, Based on Testing of Hypotheses about Regreession Models, RuhrUniversität (Bochum, 1989) [1989] :
- Research and Development of Fast Numerically Stable Algorithms for Recursive Identification of Stochastic Systems and their Fixed Point Implementations, RuhrUniversität (Bochum, 1989) [1989] :