Ing. Zdeněk Pohl, Ph.D.
Deputy head of the department
Department:
Department of Signal Processing
Research interests:
Informatics and programmable logic; parallel and extremely fast system-identification algorithms; FPGA implementations
Biography
Publication list
EU funded R&D projects partner:
- Current EU R&D projects (Chips JU):
- Listen2Future - Acoustic sensor solutions integrated with digital technologies as key enablers for emerging (HORIZON KDT JU 2023 - 2026)
- SOIL - Solidify the European FDSOI Ecosystem Accelerating its Industrial Deployment (HORIZON KDT JU 2024 - 2027)
- Past EU R&D projects:
- StorAIge (H2020 ECSEL JU, 2021 - 2024)
- Arrowhead Tools (H2020 ECSEL JU, 2019 - 2022)
- FitOptiVis (H2020 ECSEL JU, 2018 - 2021)
- WAKeMeUP (H2020 ECSEL JU, 2018 - 2021)
- Productive4.0 (H2020 ECSEL JU, 2017 - 2020)
- SILENSE (H2020 ECSEL JU, 2017 - 2020)
- THINGS2DO (FP7 ENIAC JU, 2014 - 2018)
- PANACHE (FP7 ENIAC JU, 2014 - 2018)
- EMC2 (FP7 ARTEMIS JU, 2014 - 2017)
- ALMARVI (FP7 ARTEMIS JU, 2014 - 2017)
- SCALOPES (FP7 ARTEMIS JU, 2009 - 2011)
- AETHER (FP6 ICT, 2006 - 2009)
- RECONF 2 (FP5 IST, 2002 - 2004)
CZ funded R&D projects partner:
- Past CZ R&D projects:
- Driver adaptation on Driving Assistance Systems in the vehicle (2016 - 2017)
- Development adaptive interactive system for increasing safety of vehicle crew and its use for evaluation of pavement surface characteristics (2014 - 2017)
- Virtual Laboratory of Microprocessor Technology Application (2006 - 2011)
- Rapid prototyping tools for development of HW-accelerated embedded image- and video-processing applications (2004 - 2008)
- Digital Video-Sensoric System of Reconnaissance Robot (2004 - 2007)
Journal articles
- : Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA, EURASIP Journal on Advances in Signal Processing 2008 2008 (2008), p. 1-11 Download DOI: 10.1155/2008/394201 [2008]
- : The European Logarithmic Microprocessor, IEEE Transactions on Computers 57 4 (2008), p. 532-546 Download [2008]
- : Platforma s částečnou dynamickou rekonfigurací FPGA, Automa 12 5 (2006), p. 40-43 [2006]
- : Reconfigurable System-on-a-Chip, Syndicated 5 2 (2005), p. 1-3 [2005]
- : Reconfigurable system on programmable chip platform, ATMEL Applications Journal, p. 9-12 [2005]
Other publications
- : UTIA Ultrasound EV Board v2.x for 3CG platform (2025) Download [2025]
- : Compilation of AI 3.0 models for Vitis 2023.2, AI 3.5 SW, AI 3.0 DPUCZDX8G (2024) Download [2024]
- : Support for TE0820 Modules in Vitis 2023.2, AI 3.5 SW, AI 3.0 DPUCZDX8G (2024) Download [2024]
- : Support for TE0821 Modules in Vitis 2023.2, AI 3.5 SW, AI 3.0 DPUCZDX8G (2024) Download [2024]
- : Support for STM32H573I DK V1.4.0 web server (2024) Download [2024]
- : UTIA Ultrasound EV Board v2.0 (2024) Download [2024]
- : Adaptive Lattice Filter on STM32H7 Devices (2024) Download [2024]
- : Support for TE0821 modules with Vitis AI 3.0 DPU (2024) Download [2024]
- : Support for TE0820 modules with Vitis AI 3.0 DPU (2024) Download [2024]
- : Support for STM32H573I-DK web server (2024) Download [2024]
- : Compilation of Vitis AI 3.0 models for different configurations of AMD DPUs. (2024) Download [2024]
- : Support for TE0802-02-2AEV2-A board with Vitis AI 3.0 DPU and VGA display (2024) Download [2024]
- : Support for TE0802-02-1BEV2-A board with Vitis AI 3.0 DPU and VGA display (2024) Download [2024]
- : Xilinx Vitis AI facedetect and resnet50 Demo on Trenz Electronic TE0802 02 with ZU2CG and 1 GB LPDD4 (2023) Download [2023]
- : Xilinx Vitis AI facedetect Demo on Trenz Electronic TE0820 4EV SoM with TE0701 06 Carrier Board and Avnet HDMI In/Out FMC Card (2023) Download [2023]
- : Xilinx Vitis AI 'facedetect' Demo on Trenz Electronic board TE0808 SoM + TEBF0808 Carrier (2022) Download [2022]
- : All VART Examples from Xilinx Vitis AI 2.0 for Trenz Electronic board TE0808 SoM + TEBF0808 Carrier (2022) Download [2022]
- : Testing all Samples from Xilinx Vitis AI Library 2.0 on Trenz Electronic board TE0808 SoM + TEBF0808 Carrier (2022) Download [2022]
- : Xilinx Vitis AI ‘facedetect’ and ‘resnet50’ Demo on Trenz Electronic TE0821-01-2cg-4GB SoM + TE0706-3 Carrier (2022) Download [2022]
- : STM32H753 Terminal with Zynq Ultrascale+ Accelerator (2021) Download [2021]
- : STM32H753 Terminal with TE0723 03 07S 1C Accelerator HW Data Movers (2021) Download [2021]
- : Data Movers in DTRiMC tool for TE0726 03M 07S board (2021) Download [2021]
- : DTRiMC tool for TE0820-03-4EV-1E module on TE0701-06 carrier board (2021) Download [2021]
- : DTRiMC tool for TE0820-02-3CG-1E module on TE0701-06 carrier board (2021) Download [2021]
- : DTRiMC tool for TE0808-15-EG-1EE module on TEBF0808 carrier board (2021) Download [2021]
- : Evaluation version of 8xSIMD FP01x8 accelerator for ArduZynq shield (2019) Download [2019]
- : FP01x8 Accelerator on TE0726-03M (2019) Download [2019]
- : Two serial connected evaluation versions of FP03x8 accelerators for TE0820-03-4EV-1E module on TE0701-06 carrier board. (2019) Download [2019]
- : UTIA Evaluation Board v1.7 v1.8 Beamforming Demo (2019) Download [2019]
- : UTIA evBoard v1.0 Beamforming Demo (2019) Download [2019]
- : Video Input/Output IP Cores for Xilinx ZCU102 with Avnet HDMI Input/Output FMC Module (2019) Download [2019]
- : Video Input/Output IP Cores for TE0820 SoM with TE0701 Carrier and and Avnet HDMI Input/Output FMC Module (2019) Download [2019]
- : Design Time and Run Time Resources for Zynq Ultrascale+ TE0820-03-4EV-1E with SDSoC 2018.2 Support (2019) Download [2019]
- : Design Time and Run Time Resources for Zynq Ultrascale+ TE0808-04-15EG-1EE with SDSoC 2018.2 Support (2019) Download [2019]
- : Design Time and Run Time Resources for the ZynqBerry Board TE0726-03M with SDSoC 2018.2 Support (2019) Download [2019]
- : Arrowhead Compatible Zynq Ultrascale+ Systems with Xilinx SDSoC 2018.2 Support (2019) Download [2019]
- : Arrowhead Compatible Zynq with SDSoC 2017.4 and Floating-Point 8xSIMD EdkDSP Accelerators (2019) Download [2019]
- : SILENSE TE0706+TE0720 Ultrasound Capture Platform with Example Application (2019) Download [2019]
- : Live Canny Edge Detection (2018) Download [2018]
- : Stereo Demo (2018) Download [2018]
- : Compact Zynq System 2017.4 with SW-defined Floating-Point 8xSIMD EdkDSP Accelerator (2018) Download [2018]
- : Compact Zynq System with SW-defined Floating-Point 8xSIMD EdkDSP Accelerator (2018) Download [2018]
- : SW Defined Floating Point 8xSIMD EdkDSP IP Serving for Adaptive Noise Cancellation (2018) Download [2018]
- : Video Processing Demonstrator with Full HD Sensor and 8xSIMD EdkDSP Accelerator IP Core (2018) Download [2018]
- : A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC2, Computer Safety, Reliability, and Security : SAFECOMP 2017 Workshops, ASSURE, DECSoS, SASSUR, TELERISE, and TIPS, p. 127-140, Eds: Tonetta Stefano, Schoitsch Erwin, Bitsch Friedemann Download DOI: 10.1007/978-3-319-66284-8 [2017]
- : Full HD Video Processing in HW with three EdkDSP 8xSIMD Accelerators for TE0715-30-1 SoM on TE0701-06 Carrier (2017) Download [2017]
- : Full HD Video Processing in HW with three EdkDSP 8xSIMD Accelerators for TE0715-04-30-3E SoM on TE0701-06 Carrier (2017) Download [2017]
- : Full HD Video Processing in HW with three EdkDSP 8xSIMD Accelerators for TE0715-30-1 SoM on EMC2-DP-V2 Carrier (2017) Download [2017]
- : APCP Image Processing Demos (2016) Download [2016]
- : Asymmetric Multiprocessing with MicroBlaze, EdkDSP Accelerator and Toshiba Sensor Video for Automotive grade Zynq on TE0720-03-1QF SoM on TE0701-05 Carrier (2016) Download [2016]
- : Asymmetric Multiprocessing with MicroBlaze, EdkDSP Accelerator and Toshiba Sensor Video Processing for low cost Zynq on TE0720-03-1CF SoM on TE0701-05 Carrier (2016) Download [2016]
- : EMC2-DP HDMI in HDMI out Platform (2016) Download [2016]
- : Full HD HDMI In-Out HW-Accelerated Demos for Zynq System-on-Module TE0715-03-30-1I and Sundance EMC2-DP-V2 Platform (2016) Download [2016]
- : SDSoC 2015.4 Standalone BSP with Full HD HDMI In-Out SW and HW Demos for Automotive Zynq TE0720-03-1QF Module or Commercial Zynq TE0720-03-1CF Module on TE0701-05 Carrier Board (2016) Download [2016]
- : SDSoC 2015.4 Standalone BSP with Full HD HDMI In-Out SW and HW Demos for Zynq System-on-Module TE0720-03-2IF and TE0701-05 Carrier Board (2016) Download [2016]
- : SDSoC 2015.4 Standalone BSP with Full HD HDMI In-Out with SW and HW Demos for Zynq System-on-Module TE0715-03-30 and Sundance EMC2-DP-V2 Platform (2016) Download [2016]
- : ALMARVI Python Camera Platform (2016) Download [2016]
- : Python 1300 Sensor Video Processing in HW with EdkDSP 8xSIMD Accelerator for TE0720-03-2IF SoM on TE0701-05 Carrier (2016) Download [2016]
- : Full HD HDMI In-Out HW-Accelerated Demos for Zynq System-on-Module TE0720-03-2IF and TE0701-05 Carrier Board (2016) Download [2016]
- : Zynq Platform with UTIA EdkDSP Accelerator and Toshiba Sensor Video Processing in HW for TE0720-03-2IF SoM on TE0701-05 Carrier (2016) Download [2016]
- : Full HD Toshiba Video Sensor Platform with Automotive Grade Arm Zynq on TE0720-03-1QF SoM on TE0701-05 Carrier (2016) Download [2016]
- : Toshiba Video Sensor Evaluation Platform for TE0720-03-2IF SoM on TE0701-05 Carrier (2016) Download [2016]
- : Python 1300 Video Sensor Evaluation Platform for TE0720-03-2IF SoM on TE0701-05 Carrier (2016) Download [2016]
- : Evaluation of Asymmetric Multiprocessing for Zynq System-on-Modules TE0720-02-2IF, TE0720-02-1CF, TE0720-02-1QF with Carrier Board TE0701-05 (2015) Download [2015]
- : Video Input/Output Demonstration for Trenz TE0701-05, TE0720-02-1CF, TE0720-02-1QF, TE0720-02-2IF and Avnet HDMI Input/Output FMC Module (2015) Download [2015]
- : 3D Anaglyph Demo (2015) Download [2015]
- : Dynamic Programmable Logic Reconfiguration for Zynq (2015) Download [2015]
- : Asymmetric Multiprocessing on ZYNQ ZC702 board with EdkDSP Accelerators for Xilinx Vivado 2013.4 Design Flow (2014) Download [2014]
- : Simulátor rozpoznávání pohybu v obrazech s nízkým rozlišením (2014) Download [2014]
- : DMA jednotka pro BCE v systémech s AXI sběrnicí (2012) Download [2012]
- : A Framework for Self-adaptive Collaborative Computing on Reconfigurable Platforms, Advances in Parallel Computing, p. 579-586 Download DOI: 10.3233/978-1-61499-041-3-579 [2012]
- : DSP Library for UTIA BCE platform (2011) [2011]
- : Resource Management: Implementation and performance results (2011) [2011]
- : Resource Management for the Heterogeneous Arrays of Hardware Accelerators, Proceedings of 21st International Conference on Field Programmable Logic and Applications, p. 486-489 Download [2011]
- : Reed-Solomon Coder Simulation (2009) [2009]
- : Self-adaptive LMS filter (2009) [2009]
- : Adaptive Noise Canceller Migration Demo (2008) [2008]
- : Adaptive Noise Canceller Demo based on the LS Lattice Filter (2007) Download [2007]
- : RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator, Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL), p. 774-777, Eds: Bertels Koen, Najjar Walid, Genderen Arjan, Vassiliadis Stamatis [2007]
- : Komunikace pro adm-xrc-4sx pomocí ZBIT pamětí, ÚTIA AV ČR (Praha, 2007) [2007]
- : Komunikace pro adm-xrc-4sx, ÚTIA AV ČR (Praha, 2007) [2007]
- : Double Precision System Generator Library, ÚTIA AV ČR (Praha, 2007) [2007]
- : Výstup z Celoxica DK jako BlackBox komponenta Systém Generátoru, ÚTIA AV ČR (Praha, 2007) [2007]
- : Flash Formatter, ÚTIA AV ČR (Praha, 2007) [2007]
- : RLS Lattice Demo, ÚTIA AV ČR (Praha, 2006) [2006]
- : GIN - notetaker for blind people: An example of using dynamic reconfiguration of FPGAs, ACACES 2005. Advanced Computer Architecture and Compilation for Embedded Systems, p. 15-18, HiPEAC Network of Excellence (Ghent, 2005) [2005]
- : Figaro: An automatic tool flow for designs with dynamic reconfiguration. Abstract, FPGA 2005 - ACM/SIGDA Thirteenth ACM International Symposium on Field-Programmable Gate Arrays, p. 262, Eds: Schmidt H., Wilton S., ACM (Monterey, 2005) [2005]
- : Performance tuning of interative algorithms in signal processing, Proseedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005, p. 699-702, Eds: Rissa T., Wilton S., Leong P. [2005]
- : Figaro - an automatic tool flow for designs with dynamic reconfiguration, Proceedings of the 2005 International Conference on Field Programmable Logic and Applications. FPL 2005, p. 590-593, Eds: Rissa T., Wilton S., Leong P. [2005]
- : Scheduling of iterative algorithms on FPGA with pipelined arithmetic unit, Real-Time and Embedded Technology and Applications Symposium, p. 404-412 Download [2004]
- : ADPCM IP Cores, ÚTIA AV ČR (Praha, 2004) [2004]
- : ADPCM Demo, ÚTIA AV ČR (Praha, 2004) [2004]
- : Reconfigurable system-on-a-programmable-chip platform, Proceedings of the 7th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, p. 21-28 [2004]
- : Logarithmic arithmetic for real data types and support for Matlab/Simulink based rapid-FPGA-prototyping, Proceedings of the International Parallel and Distributed Processing Symposium. IPDPS 2003, p. 1-6, IEEE Computer Society Press (Los Alamitos, 2003) [2003]
- : Logarithmic number system and floating-point arithmetics an FPGA, Počítačové Architektury & Diagnostika PAD 2003, p. 9-16, Eds: Kotásek Z., Růžička R., Sekanina L., VUT (Brno, 2003) [2003]
- : Lattice IP Core used in Real-time Lattice Demo on XESS Board. (Program), ÚTIA AV ČR (Praha, 2003) [2003]
- : RLS Lattice - Celoxica RC200 Demo. (Program), ÚTIA AV ČR (Praha, 2003) [2003]
- : Dynamic reconfiguration of Atmel FPGAs, UK ACM SIGDA 3rd Workshop on Electronic Design Automation, p. 1-4, University of Southampton (Southampton, 2003) [2003]
- : Dynamic reconfiguration of FPGAs, Recent Trends in Multimedia Information Processing. Proceedings, p. 288-291, Eds: Šimák B., Zahradník P., Czech Technical University (Prague, 2003) [2003]
- : FPGA implementation of the adaptive lattice filter, Field-Programmable Logic and Applications. Proceedings of the 13th International Conference, p. 1095-1098, Eds: Cheung P. Y. K., Constantinides G. A., de Sousa J. D., Springer (Berlin, 2003) [2003]
- : Dynamic runtime partial reconfiguration in FPGA, ECMS 2003. 6th International Workshop on Electronics, Control, Measurement and Signals, p. 294-298, Eds: Nouza J., Drábková J., Technical University (Liberec, 2003) [2003]
- : Lattice adaptive filter implementation for FPGA, FPGA 2003 ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, p. 246, ACM (Monterey, 2003) [2003]
- : Logarithmic Arithmetic for Real Data Types and Support for MATLAB/SIMULINK Based Rapid-FPGA-Prototyping, ÚTIA AV ČR (Praha, 2002) [2002]
- : Utilization of the HSLA toolbox for the FPGA prototyping, MATLAB 2002. Sborník příspěvků 10. ročníku konference, p. 462-468, VŠCHT (Praha, 2002) [2002]
- : Logarithmic number system and floating-point arithmetics on FPGA, Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, p. 627-636, Eds: Glesner M., Zipf P., Renovell M., Springer (Berlin, 2002) [2002]
- : Prototyping of DSP algorithms on FPGA, POSTER 2002, p. 2, FEL ČVUT (Praha, 2002) [2002]
- : The European Logarithmic Microprocessor - a QRD RLS Applications, ÚTIA AV ČR (Praha, 2001) [2001]
- : Utilization of Matlab for the logarithmic processor development, Sborník příspěvků 9.ročníku konference MATLAB 2001, p. 222-225, Eds: Procházka A., Uhlíř J., VŠCHT (Praha, 2001) [2001]
- : Tuning and implementation of DSP algorithms on FPGA, Sborník příspěvků 9.ročníku konference MATLAB 2001, p. 226-230, Eds: Procházka A., Uhlíř J., VŠCHT (Praha, 2001) [2001]
- : Pipelined logarithmic 32bit ALU for Celoxica DK1, Sborník příspěvků 9.ročníku konference MATLAB 2001, p. 72-80, Eds: Procházka A., Uhlíř J., VŠCHT (Praha, 2001) [2001]